The present invention relates to a semiconductor device and a manufacturing method therefor, and, more particularly, to an effective technique applicable to a semiconductor device including a fin transistor.
The fin transistor is known as a field effect transistor, which has a high operation speed, and can reduce the leakage current and consumption power and can realize miniaturization of the semiconductor element. The fin transistor (FINFET: FIN Field Effect Transistor) is a semiconductor element, having, for example, a semiconductor layer which projects over the semiconductor substrate as a channel region and having a gate electrode which is formed across and over the projecting semiconductor layer.
As an electrically writable and erasable non-volatile memory, a flash memory and an EEPROM (Electrically Erasable and Programmable Read Only Memory) are widely used. These memory units have, below the gate electrode MISFET (Metal Insulator Semiconductor Field Effect Transistor), a conductive floating gate electrode surrounded by an oxide film or a trap insulating film, assume a charge storage state in the floating gate or the trap insulating film as storage information, and read it as a threshold value of the transistor. This trap insulating film represents a charge storage insulating film, and is, for example, a silicon nitride film. Injection and discharge of charges to and from this charge storage layer cause the threshold value of the MISFET to shift, and cause it to operate as a storage element. This flash memory is also called a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) transistor. The MONOS transistor is used as a transistor for memory. Further, a split gate-type memory cell with a transistor for controlled added thereto is widely used.
U.S. Unexamined Patent Application Publication No. 2011/0001169 discloses a technique for forming a silicide layer on a surface of the fin, in the FINFET.
Japanese Unexamined Patent Application Publication No. 2011-210790 discloses a technique for suppressing abnormal growth of a silicide layer, by performing a heating process twice to form the silicide layer covering the surface of a source region and the surface of a drain region.
Japanese Unexamined Patent Application Publication No. 2006-041354 discloses a technique for forming a silicide layer covering the surface of the fin, when a split gate-type memory cell including a MONOS transistor is configured with a FINFET structure.